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	<updated>2026-04-04T17:44:35Z</updated>
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		<title>Elijah: Created page with &quot;== XDMAC Setup == There are a few aspects of the ATSAMV71 XDMAC which I found confusing with respect to using it to transfer to/from peripherals.   * When doing an RX operatio...&quot;</title>
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		<updated>2024-08-28T21:19:10Z</updated>

		<summary type="html">&lt;p&gt;Created page with &amp;quot;== XDMAC Setup == There are a few aspects of the ATSAMV71 XDMAC which I found confusing with respect to using it to transfer to/from peripherals.   * When doing an RX operatio...&amp;quot;&lt;/p&gt;
&lt;p&gt;&lt;b&gt;New page&lt;/b&gt;&lt;/p&gt;&lt;div&gt;== XDMAC Setup ==&lt;br /&gt;
There are a few aspects of the ATSAMV71 XDMAC which I found confusing with respect to using it to transfer to/from peripherals. &lt;br /&gt;
&lt;br /&gt;
* When doing an RX operation, that is transferring data from a peripheral into memory, the source address must be set to the memory address of the peripheral&amp;#039;s read data register. For example when using SPI, you would need to set the source address to SPI_RDR. I found this a bit confusing since you also have to specify the ID of the peripheral involved - so I imagined that would automatically let it know where to read/write from. &lt;br /&gt;
&lt;br /&gt;
* Same on the TX side, the destination address must be set to the peripheral&amp;#039;s transmit data register. &lt;br /&gt;
&lt;br /&gt;
* When using the XDMAC in linked list mode:&lt;br /&gt;
# Setup a global array of descriptors, with each descriptor aligned to 64 byte boundaries.&lt;br /&gt;
# Set one of those descriptors up as desired for your channel. This is described pretty straightforward in the data sheet. &lt;br /&gt;
# Note the similarity between the descriptor&amp;#039;s microblock control word and the channel&amp;#039;s XDMAC_CNDC. The NDDUP NDSUP bits in XDMAC_CNDC should most likely always be set if you are using anything except &amp;quot;View 0&amp;quot;. Otherwise, the XDMAC will not copy the descriptor source and destination address into the channel&amp;#039;s source and destination address, which is what you probably expect it to do. &lt;br /&gt;
&lt;br /&gt;
* You can debug the linked list behavior somewhat by watching if the source and dest address get copied from the descriptor into XDMAC_CSAx/XDMAC_CDAx when you enable the channel. Setting the bit in XDMAC_GE is what turns the DMA channel loose to start running - hardware will pace it as data is ready if you&amp;#039;re doing a peripheral transfer though.&lt;/div&gt;</summary>
		<author><name>Elijah</name></author>
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